Electrode in semiconductor device, capacitor and method of fabricating the same

ABSTRACT

A semiconductor device and a method of fabricating the same include an electrode having a nickel layer with impurities. The electrode having a nickel layer with impurities can be a gate electrode or a capacitor electrode. The electrode having a nickel layer with impurities may include a combination of a pure nickel layer and a nickel layer with impurities.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a Divisional Application of U.S. patentapplication Ser. No. 12/344,182, filed Dec. 24, 2008, which claimspriority of Korean patent application number 2008-0081575, filed on Aug.20, 2008, which is incorporated herein by reference in its entirety.

BACKGROUND

The disclosure relates to a semiconductor device, and more particularly,to an electrode and a capacitor in a semiconductor device, and a methodof fabricating the same.

Recently, in a process for fabricating a Metal Insulator Metal (MIM)capacitor, a method for fabricating a dielectric layer with a highdielectric constant (k) or an electrode having a high work function hasbeen proposed to obtain required capacitance even when a semiconductordevice is integrated.

However, the dielectric layer with the high dielectric constant (k)cannot be applied to semiconductor devices due to deterioration ofcurrent leakage despite the fact that the dielectric layer with the highdielectric constant (k) has a low energy band gap.

To overcome the limitation of the dielectric layer, precious metals areused to form the electrode. However, the precious metal cannot beapplied to the process since the precious metal with a high workfunction has a low adhesion force due to a low coupling force.

Thus, it is required to develop an electrode with the high work functionand the high adhesion force.

SUMMARY

One or more embodiments provide a semiconductor device having anelectrode and/or a capacitor and method of fabricating the same.

In accordance with one or more embodiments, an electrode for asemiconductor device includes a nickel layer with impurities.

The impurities may include carbon (C) or hydrogen (H). The concentrationof the impurities in the nickel layer with impurities may range fromapproximately 5% to approximately 50%.

In accordance with one or more embodiments, an electrode for asemiconductor device includes a combination of a pure nickel layer and anickel layer with impurities.

The pure nickel layer and the nickel layer with impurities may be formedto have a stack structure.

The combination of the pure nickel layer and the nickel layer withimpurities may have a stack structure of a nickel layer with impurities,a pure nickel layer, and a nickel layer with impurities.

In accordance with one or more embodiments, a capacitor includes: afirst electrode; a dielectric layer; and a second electrode, wherein oneof the first electrode and the second electrode includes a nickel layerwith impurities.

One of the first electrode and the second electrode may include a purenickel layer and a nickel layer with impurities.

The nickel layer with impurities may be formed to be in contact with thedielectric layer.

One of the first electrode and the second electrode may have a stackstructure of a nickel layer with impurities, a pure nickel layer, and anickel layer with impurities.

One of the first electrode and the second electrode may have a stackstructure of a pure nickel layer and a nickel layer with impurities.

The impurities may include carbon (C) or hydrogen (H).

The concentration of the impurities in the nickel layer with impuritiesmay range from approximately 5% to approximately 50% of the nickel layerwith impurities.

The first electrode or the second electrode may be of a concave type, acylinder type, or a pillar type.

In accordance with one or more embodiments, a method of fabricating acapacitor includes: forming a first electrode; forming a dielectriclayer over the first electrode; and forming a second electrode over thedielectric layer, wherein one of the first electrode and the secondelectrode includes a nickel layer with impurities.

The impurities may include carbon (C) or hydrogen (H).

The concentration of the impurities in the nickel layer with impuritiesmay range from approximately 5% to approximately 50%.

One of the first electrode and the second electrode may have acombination of a pure nickel layer and a nickel layer with impurities.

The nickel layer with impurities may be formed to be in contact with thedielectric layer.

One of the first electrode and the second electrode may have a stackstructure of a pure nickel and a nickel layer with impurities.

The first electrode or the second electrode may have a stack structureof a nickel layer with impurities, a pure nickel layer, and a nickellayer with impurities.

The pure nickel layer and the nickel layer with impurities may be formedthrough a Chemical Vapor Deposition (CVD) process or an Atomic LayerDeposition (ALD) process.

The pure nickel layer and the nickel layer with impurities may be formedthrough the ALD process using a nickel precursor and a reaction gas.

The nickel precursor may flow at a rate of approximately 50 sccm to1,000 sccm. The reaction gas may flow at a rate of approximately 100sccm to approximately 3,000 sccm for formation of the nickel layer withimpurities, and the reaction gas may flow at a rate of approximately3,000 sccm to approximately 5,000 sccm for formation of the pure nickellayer.

The reaction gas may include H₂ or NH₃.

H₂ plasma or NH₃ plasma may be applied during the ALD process.

The ALD process may be performed at a temperature of approximately 200°C. to approximately 500° C.

The pure nickel layer and the nickel layer with impurities may be formedIn-situ or Ex-situ.

The first electrode or the second electrode may be of a concave type, acylinder type or a pillar type.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view illustrating an electrode in accordancewith an embodiment.

FIGS. 2A to 2C are cross-sectional views illustrating a method forfabricating the electrode in accordance with one or more embodiments.

FIG. 3 is a timing diagram illustrating a method for forming theelectrode in accordance with an embodiment.

FIG. 4 is a cross-sectional view illustrating a capacitor in accordancewith an embodiment.

FIG. 5 is a cross-sectional view illustrating a cylinder type capacitorin accordance with an embodiment.

FIGS. 6A to 6E are cross-sectional views illustrating a method forfabricating a cylinder type capacitor in accordance with an embodiment.

FIG. 7 is a cross-sectional view illustrating a pillar type capacitor inaccordance with an embodiment.

FIGS. 8A to 8E are cross-sectional views illustrating a method forfabricating a pillar type capacitor in accordance with an embodiment.

DESCRIPTION OF EMBODIMENTS

One or more embodiments relate to an electrode and/or a capacitorelectrode in a semiconductor device, and a method of fabricating thesame. In accordance with one or more embodiments, an electrode includesa nickel layer containing impurities, such as carbon (C) or hydrogen(H), to improve adhesion force. Furthermore, leakage currentcharacteristics and crystallization characteristics of a dielectriclayer can be improved.

The advantages, features and aspects of one or more embodiments willbecome apparent from the following description of the embodiments withreference to the accompanying drawings.

In the drawings, the illustrated thicknesses of layers and regions areexaggerated to facilitate explanation. It will also be understood thatwhen a layer is referred to as being “on/under” another layer orsubstrate, it can be directly on/under the other layer or substrate, orintervening layers may also be present. In addition, when a layer isreferred to as being ‘between’ two layers, it can be the only layerbetween the two layers, or one or more intervening layers may also bepresent. Furthermore, the same or like reference numerals represent thesame or like elements throughout the drawings.

FIG. 1 is a cross-sectional view illustrating an electrode in accordancewith an embodiment.

Referring to FIG. 1, an electrode with a nickel layer containingimpurities in a semiconductor device is formed. The electrode may beapplied to a gate electrode or at least one of upper and lowerelectrodes of a capacitor. The electrode may be applied to any otherdevices employing a high dielectric layer.

The nickel layer has a high work function of approximately 4.8 eV toapproximately 5.15 eV and exhibits excellent adhesion force with otherlayers. Thus, when the nickel layer is used as an electrode of thedevice with the high dielectric layer, current leakage characteristicscan be improved.

A pure nickel layer has poor roughness because of a three-dimensionalstructure growth and may be oxidized during a process of depositing adielectric layer over the pure nickel layer. According to an embodiment,a nickel layer 101 containing impurities can improve the roughness andprevent the oxidation.

The impurities in the nickel layer 101 do not affect the characteristicsof the pure nickel layer. Preferably, the impurities may be carbon (C)or hydrogen (H). The impurities may range from approximately 5% toapproximately 50% of the nickel layer 101.

The nickel layer 101 containing impurities, for example, a nickel layer101 containing carbon (C), is formed to have Ni—C coupling and grows ina two-dimensional direction so that the nickel layer 101 has a planarsurface. The Ni—C coupling enables Ni and C to combine with each otherand therefore, the nickel layer 101 containing carbon (C) has lesscrystallization characteristics than the pure nickel layer, and carbon(C) is randomly distributed and deposited in the nickel layer 101. Thus,the nickel layer 101 firstly grows in the second-dimensional directionto form the planar surface and then a deposition process is performedforming a film layer with the planar surface.

Since the nickel layer 101 containing the impurities has relatively lesschemical bondings between Ni and C than the pure nickel layer due to thepresence of the impurities, the oxidation is prohibited.

FIGS. 2A to 2C are cross-sectional views illustrating a method forfabricating the electrode in accordance with another embodiment.

Referring to FIG. 2A, an electrode with a stack structure of a firstnickel layer 201 containing impurities, a pure nickel layer 202, and asecond nickel layer 203 containing impurities is formed. The electrodecan be applied to a gate electrode or at least one of an upper electrodeand a lower electrode of a capacitor. The electrode may be used as anelectrode in any other device employing a high dielectric layer.

The pure nickel layer 202 has a high work function of approximately 4.8eV to approximately 5.15 eV and exhibits excellent adhesion force withother layers. Thus, when the nickel layer is employed as an electrode ofthe device with the high dielectric layer, current leakagecharacteristics can be improved.

The first nickel layer 201 containing impurities and the second nickellayer 203 containing impurities are formed to improve the roughness andprevent the oxidation.

The impurities in the first and second nickel layers 201 and 203containing impurities do not affect the quality of the pure nickel layer202. Preferably, the impurities may be carbon (C) or hydrogen (H). Whena ratio of C to Ni is 1:3, that is, when a compound contains C ofapproximately 25% and Ni of approximately 75%, the compound is called aNickel carbide (Ni₃C).

Since the pure nickel layer 202 grows in a three-dimensional direction,the surface roughness is not excellent. However, the first and secondnickel layers 201 and 203 containing the impurities, for example, havinga Ni—C coupling, grow in a second-dimensional direction, forming aplanar surface.

In the Ni—C coupling, Ni and C are combined with each other. Therefore,the first and second nickel layers 201 and 203 containing the impuritieshave less crystallization than the pure nickel layer 202 and theimpurities are randomly distributed. Thus, the nickel layer 201 firstlygrows in the second-dimensional direction to form a planar surface andthen a deposition process is performed. Thus, a film layer with theplanar surface is formed.

Since the first and second nickel layers 201 and 203 containing theimpurities has relatively less chemical bondings than the pure nickellayer because of the Ni—C coupling, the oxidation is prevented.

The electrode with a stack structure comprising the first nickel layer201 containing impurities, the pure nickel layer 202, and the secondnickel layer 203 containing impurities is formed in a planar type.However, the electrode with a stack structure comprising the firstnickel layer 201 containing impurities, the pure nickel layer 202, andthe second nickel layer 203 containing impurities can be formed to havea plate type, a concave type, a cylinder type, a pillar type and acombination thereof.

The first nickel layer 201 containing impurities, the pure nickel layer202, and the second nickel layer 203 containing impurities are formedthrough a Chemical Vapor Deposition (CVD) process or an Atomic LayerDeposition (ALD) process. The formation method through the ALD processwill be described in more detail later by referring to FIG. 3.

Referring to FIG. 2B, an electrode with a stack structure of a purenickel layer 211 and a nickel layer 212 containing impurities may beformed. The electrode can be applied to a gate electrode or at least oneof an upper electrode and a lower electrode of a capacitor. Theelectrode may be applied to any other devices employing a highdielectric layer. Preferably, the stack structure of the pure nickellayer 211 and the nickel layer 212 containing the impurities may beapplied to the lower electrode in the planar type capacitor.

Referring to FIG. 2C, an electrode with a stack structure of a nickellayer 221 containing impurities and a pure nickel layer 222 may beformed. The electrode can be applied to a gate electrode or at least oneof an upper electrode and a lower electrode of a capacitor. Theelectrode may be applied to any other devices employing a highdielectric layer. Particularly, the stack structure of the nickel layer221 containing the impurities and the pure nickel layer 222 may beapplied to the upper electrode of a planar type capacitor.

FIG. 3 is a timing diagram illustrating a method for forming theelectrode in accordance with an embodiment. The method for forming theelectrode illustrated in FIG. 2A will be described referring to FIG. 3hereafter for the sake of convenience in explaining the embodiments.

According to the ALD process, a source gas is provided to be chemicallyadsorbed to a surface of a substrate, and a purge gas flows to purge thephysically extra-adsorbed sources. A reaction gas is provided to asource in one layer to cause a chemical reaction between the source inone layer and the reaction gas to thereby deposit an atomic film layer.The ALD process is performed in a surface reaction mechanism to form astable and even film layer. Thus, the method can be applied to a processfor forming a structure with high step coverage (or a big heightdifference) and a low design rule.

Furthermore, since the source gas and the reaction gas are separated,sequentially provided and purged, the ALD process generates lessparticles caused by a gas phase reaction than the CVD process.

Referring to FIG. 3, the first nickel layer containing the impurities,the pure nickel layer, and the second nickel layer containing theimpurities are formed in sequence through the ALD process.

Herein, each layer is formed in-situ or ex-situ. Particularly, when thelayer is formed in-situ, the quantity of the reaction gas for formingthe layer is controlled to form the pure nickel layer, the first nickellayer containing the impurities and the second nickel layer containingthe impurities. For instance, when the source gas flows at a rate ofapproximately 50 sccm to approximately 1,000 sccm, the reaction gas iscontrolled to flow at a rate of approximately 3,000 to approximately5,000 sccm to form the pure nickel layer and at a rate of approximately100 sccm to approximately 3,000 sccm to form the first and the secondnickel layers.

First to third unit cycles are sequentially performed to form the firstnickel layer containing the impurities, the pure nickel layer, and thesecond nickel layer containing impurities. Particularly, each unit cycleis repeatedly performed X, Y, and Z times, respectively to adjustthicknesses of the above layers.

The ALD process may be performed at a temperature of approximately 200°C. to approximately 500° C.

Each of the first to third unit cycles is performed in a sequence ofsource gas/purge gas/reaction gas/purge gas.

The first unit cycle for forming the first nickel layer containing theimpurities includes injection of nickel source gas 301, injection ofpurge gas 302, injection of reaction gas 303, and injection of purge gas302.

The injection of the nickel source gas 301 flows nickel organicprecursor at a rate of approximately 50 sccm to approximately 1,000 sccmfor approximately 0.1 second to approximately 10 seconds by usingcarrier gas such as nitrogen (N₂) or argon (Ar). Here, the nickelorganic precursor may be NiCO₃.

The injection of the purge gas 302 is performed after the injection ofthe source gas 301 and the injection of the reaction gas 303. In theinjection of the purge gas 302, the N₂ gas flows into a depositionchamber at a rate of approximately 100 sccm to approximately 2,000 sccmfor approximately 1 second to approximately 10 seconds to remove theremaining nickel source gas or reaction gas in the chamber.

The injection of the reaction gas 303 is performed to form the firstnickel layer containing the impurities. The reaction gas, that is, H₂ orNH₃ flows into the deposition chamber at rate of approximately 100 sccmto approximately 3,000 sccm for 1 second to 10 seconds to form the firstnickel layer containing the impurities. Particularly, the reaction gasis adjusted to form the first nickel layer containing the impurities.Here, the reaction gas is injected less than that required for formingthe pure nickel layer to prevent the reaction of the impurities in thenickel source gas. A portion of the impurities is removed and theremaining impurities are included in the film layer. Thus, the firstnickel layer containing the impurities is formed.

As described above, the first unit cycle is repeatedly performed X timesto form the first nickel layer containing the impurities with a desiredthickness.

The second unit cycle for forming the pure nickel layer includesinjection of nickel source gas 301, injection of purge gas 302,injection of reaction gas 303, and injection of purge gas 302.

The injection of the nickel source gas 301 flows nickel organicprecursor at a rate of approximately 50 sccm to approximately 1,000 sccmfor approximately 0.1 second to approximately 10 seconds by usingcarrier gas such as N₂ or Ar. Here, the nickel organic precursor may beNiCO₃.

The injection of the purge gas 302 is performed after the injection ofthe source gas 301 and the injection of the reaction gas 303. In theinjection of the purge gas 302, the N₂ gas flows into a depositionchamber at a rate of approximately 100 sccm to approximately 2,000 sccmfor approximately 1 second to approximately 10 seconds to remove theremaining nickel source gas or reaction gas in the chamber.

The injection of the reaction gas 303 is performed to form the purenickel layer. The reaction gas, which is H₂ or NH₃, flows into thedeposition chamber at rate of approximately 3,000 sccm to approximately5,000 sccm for 1 second to 10 seconds to form the pure nickel layercontaining the impurities. Particularly, the reaction gas is adjustedsufficiently to form the pure nickel layer. Here, the reaction gas isinjected in a sufficient amount that all the impurities in the nickelsource gas react off. Therefore, the reaction gas is injected in a rateof approximately 3,000 sccm to approximately 5,000 sccm.

A second unit cycle described above is repeatedly performed Y times toform the pure nickel layer with a desired thickness.

The second nickel layer containing the impurities is formed in the sameorder that the first nickel layer containing the impurities is formed.

The second nickel layer containing the impurities is formed byrepeatedly performing a third unit cycle Z times.

Particularly, each of the first to third unit cycles is repeatedlyperformed X, Y, and Z times to adjust the thickness of each layer andsequentially performed in order of stack.

Furthermore, in the ALD process, N₂ or NH₃ plasma may be applied toincrease the deposition speed.

FIG. 4 is a cross-sectional view illustrating a capacitor in accordancewith an embodiment.

Referring to FIG. 4, a capacitor with a stack structure of a firstelectrode 401, a dielectric layer 402, and a second electrode 403 isformed. Here, the first electrode 401 and the second electrode 403 mayinclude the nickel layer containing the impurities described abovereferring to FIG. 1. The first electrode 401 and the second electrode403 may be formed to have a combination of the nickel layer containingthe impurities and the pure nickel layer. The combination of the nickellayer containing the impurities and the pure nickel layer may include astack structure described above referring to FIGS. 2A to 2C.

Here, the impurities include carbon (C) or hydrogen (H). The impuritiesoccupy approximately 5% to approximately 50% of the nickel layer.

The first and the second electrodes 401 and 403 are formed through theCVD process or the ALD process.

The first and the second electrodes 401 and 403 can be formed to have aplate type, a pillar type, a concave type, a cylinder type, or acombination thereof.

FIG. 5 is a cross-sectional view illustrating a cylinder type capacitorin accordance with an embodiment.

Referring to FIG. 5, an inter-layer dielectric layer 502 is formed overa substrate 501. A storage node contact plug 503 is formed through theinter-layer dielectric layer 502 to be connected to a region in thesubstrate 501. An etch stop layer 504 is formed over the inter-layerdielectric layer 502 and patterned to open the storage node contact plug503. A cylinder type lower electrode 507A is formed over the storagenode contact plug 503. A dielectric layer 508 is formed over thecylinder type lower electrode 507A. A first upper electrode 509 and asecond upper electrode 510 are formed over the dielectric layer 508.

The cylinder type lower electrode 507A and the first upper electrode 509are formed of the nickel layer containing the impurities described abovereferring to FIG. 1 or the combination of the nickel layer containingthe impurities and the pure nickel layer described above referring toFIGS. 2A to 2C. Preferably, the cylinder type lower electrode 507A andthe first upper electrode 509 are formed to have the structureillustrated in FIG. 2A.

The dielectric layer 508 may include a high-k material. The high-kmaterial may include TiO₂, SrTiO₂, or BaSbTiO₃. Here, the lowerelectrode 507A is preferably formed to have the structure illustrated inFIG. 2A. Thus, an adhesion force of the lower electrode 507A with thedielectric layer 508 is improved and the crystal growth of thedielectric layer 508 is also improved. Further, during the dielectriclayer 508 is deposited, the lower electrode 207A is not oxidized.

FIGS. 6A to 6E are cross-sectional views illustrating a method forfabricating a cylinder type capacitor in accordance with an embodiment.

Referring to FIG. 6A, an inter-layer dielectric layer 502 is formed overa substrate 501. The substrate 501 may be a semiconductor substratewhere a DRAM process is performed or a substrate where a certain processfor forming gate patterns or bit line patterns is completed. Theinter-layer dielectric layer 502 insulates the substrate 501 from theupper capacitor. The inter-layer dielectric layer 502 may includes anoxide layer of an HDP (High Density Plasma) oxide layer, a BPSG (BoronPhosphorus Silicate Glass) layer, a PSG (Phosphorus Silicate Glass)layer, a BSG (Boron Silicate Glass) layer, a TEOS (Tetra Ethyle OrthoSilicate) layer, an USG (Un-doped Silicate Glass) layer, an FSG(Fluorinated Silicate Glass) layer, a CDO (Carbon Doped Oxide) layer, anOSG (Organo Silicate Glass) layer or a combination thereof such as astack structure including one or more of the foregoing. The oxide layermay include a layer coated by a spin coating method such as an SOD (SpinOn Dielectric) layer.

A storage node contact plug 503 through the inter-layer dielectric layer502 is formed to be connected to a region in the substrate 501. To bespecific, the inter-layer dielectric layer 502 is etched to form acontact hole exposing the substrate 501. A conductive material is formedto fill the contact hole and then an etch process is performed until thesurface of the inter-layer dielectric layer 502 is exposed.

The conductive material may include a transition metal layer, a rareearth metal layer, a transition metal silicide, a rare earth metalsilicide, or an alloy thereof. The conductive material may include apolysilicon layer doped with impurity ions or have a stack structure ofmulti-layers. The conductive material may include a stack structure ofat least two materials including the above conductive materials. Whenthe storage node contact plug 503 includes a metal layer (which is thetransition layer or the rare earth metal), a barrier metal layer (notshown) may be formed between the metal layer of storage node contactplug 503 and the contact hole.

An etch stop layer 504 is formed over the inter-layer dielectric layer502. When the contact hole for a subsequent lower electrode is formed,the etch stop layer 504 stops the etch process to prevent theinter-layer dielectric layer 502 from being damaged. Furthermore, when adip-out process for forming the cylinder type capacitor is performed,the etching solution is prevented from flowing into the inter-layerdielectric layer 502 by the etch stop layer 504. Thus, the etch stoplayer 504 includes a material having an etch selectivity ratio with asubsequent sacrificial layer. The etch stop layer 504 may include anitride layer such as a silicon nitride (SiN, Si₃N₄).

A sacrificial layer 505 is formed over the etch stop layer 504. In thesacrificial layer 505, a contact hole for the lower electrode is formed.The sacrificial layer 505 may include an oxide layer and may compriseone or more layers. The oxide layer may be an HDP oxide layer, a BPSGlayer, a PSG layer, a BSG layer, a TEOS layer, an USG layer, an FSGlayer, a CDO layer, an OSG layer or a combination thereof such as astack structure of the foregoing. The oxide layer may include a layercoated by a spin coating method such as an SOD layer.

The sacrificial layer 505 and the etch stop layer 504 are etched to forma storage node hole 506 exposing the storage node contact hole 503. Thestorage node hole 506 defines a region where the lower electrode isformed. In detail, mask patterns are formed over the sacrificial layer505, then the sacrificial layer 505 and the etch stop layer 504 areetched using the mask patterns as an etch barrier to form the storagenode hole. For mask patterns, a photoresist layer is coated over thesacrificial layer 505 and patterned to open the region where the storagenode contact hole is formed. A hard mask layer may be additionallyformed before the photoresist layer is formed to secure an etch margin,which may not be sufficient only with the photoresist layer.

Referring to FIG. 6B, a lower electrode 507 including the nickel layercontaining the impurities is formed over the resultant structureincluding the storage node hole 506. The lower electrode 507 includingthe nickel layer containing the impurities is formed through a CVDprocess or an ALD process. Preferably, the ALD process is performed tobe applied to a structure having high step coverage or a big heightdifference. Thus, the ALD process in the timing diagram illustrated inFIG. 3 can be applied to form the structures described above referringto FIGS. 2A to 2C. Preferably, the lower electrode 507 is formed to havethe structure illustrated in FIG. 2A to form the cylinder typecapacitor.

The lower electrode 507 containing the impurities includes a firstnickel layer containing impurities, a pure nickel layer, and a secondnickel layer containing impurities as the structure illustrated in FIG.2A. The pure nickel layer exhibits a high work function, low leakagecurrent and an excellent adhesion force with other layers. Furthermore,the first and second nickel layers with the impurities are formed overand below the pure nickel layer. Thus, surface roughness of the purenickel layer is improved and the surface oxidation during a subsequentdielectric layer formation process is prohibited.

A thermal treatment process is performed on the lower electrode 507 toincrease crystallinity. The thermal treatment process may be a rapidthermal treatment process or furnace annealing process. A temperaturefor the thermal treatment process varies according to equipment. In thisembodiment, the thermal treatment process is performed at a temperatureof approximately 400 to approximately 800.

Referring to FIG. 6C, a lower electrode pattern 507A remains in thestorage node hole 506, for example, by a planarization process. Theplanarization process may be a Chemical Mechanical Polishing (CMP)process or etch back process.

Referring to FIG. 6D, the sacrificial layer 505 (refer to FIG. 6C) isremoved through a dip-out process. The dip-out process is performedusing a Buffered Oxide Etchant (BOE) or Hydrogen Fluoride (HF). The etchstop layer 504 prevents the BOE or the HF from flowing into theinter-layer dielectric layer 502, thereby preventing a damage to theinter-layer dielectric layer 502 caused by the dip-out process. As aresult, the cylinder type lower electrode 507A is formed.

Referring to FIG. 6E, a dielectric layer 508 is formed over theresultant structure of FIG. 6D including the lower electrode 507A. Thedielectric layer 508 may include a high dielectric material including,but not limited to, TiO₂, SrTiO₂ or BaSbTiO₃. The dielectric constant(k) of TiO₂ is 60 to 100, that of SrTiO₂ is 80 to 100 and that ofBaSbTiO₃ is 100 to 300. TiO₂, SrTiO₂ and BaSbTiO₃ have a low energy bandgap and a high dielectric constant. As described above referring to FIG.6B, the lower electrode 507 containing the impurities exhibits excellentadhesion force, a high work function and improved surface roughness andoxidation characteristics of the pure nickel layer. Thus, adeterioration of the dielectric layer 508 with the high-k can beimproved. Furthermore, crystallinity of the dielectric layer 508 canalso be improved by the improved adhesion force.

Thereafter, a first upper electrode 509 and a second upper electrode 510are formed over the dielectric layer 508. The first upper electrode 509is formed by the same manner as that for forming the lower electrodepattern 507A. That is, the first upper electrode 509 is formed toinclude the nickel layer containing the impurities. After the formationof the first upper electrode 509, a thermal treatment process can beperformed for the same reason as the thermal treatment of the lowerelectric 507A.

The second upper electrode 510 includes a titanium nitride (TiN) layerto be electrically connected. The second upper electrode 510 may beformed through the CVD process. The upper electrode may comprise onlythe first upper electrode 509 without forming the second upper electrode510.

FIG. 7 is a cross-sectional view illustrating a pillar type capacitor inaccordance with another embodiment.

Referring to FIG. 7, an inter-layer dielectric layer 602 is formed overa substrate 601. A storage node contact plug 603 passing through theinter-layer dielectric layer 602 is formed to be connected to a regionthe substrate 601. An etch stop layer 604 is formed over the inter-layerdielectric layer 602 and patterned to open the storage node contact plug603. A pillar type lower electrode 607A is formed over the storage nodecontact plug 603. A dielectric layer 608 is formed over the pillar typelower electrode 607A over which an upper electrode 609 is formed.

The pillar type lower electrode 607A and the upper electrode 609 may beformed to have the structure illustrated in FIG. 1 or FIGS. 2A to 2C.Preferably, the pillar type lower electrode 607A may be formed to havethe structure illustrated in FIG. 2A.

The dielectric layer 608 may include a high-k material. The high-kmaterial may include TiO₂, SrTiO₂, or BaSbTiO₃. Here, the lowerelectrode 607A is formed to have the structure illustrated in FIG. 2A.Thus, an adhesion force of the lower electrode 607A with the dielectriclayer 608 is improved and the crystal growth of the dielectric layer 608is also improved. Further, during the dielectric layer 608 is deposited,the lower electrode 607A is not oxidized.

FIGS. 8A to 8E are cross-sectional views illustrating a method forfabricating a pillar type capacitor in accordance with an embodiment.The same reference numerals of FIG. 7 are used in FIGS. 8A to 8E for thesake of convenience in description.

Referring to FIG. 8A, an inter-layer dielectric layer (ILD) 602 isformed over a substrate 601. The substrate 601 may be a semiconductorsubstrate where a DRAM process is performed or a substrate where acertain process for forming gate patterns or bit line patterns iscompleted. The inter-layer dielectric layer 602 insulates the substrate601 from the upper capacitor. The inter-layer dielectric layer 602 mayinclude an oxide layer of an HDP oxide layer, a BPSG layer, a PSG layer,a BSG layer, a TEOS layer, an USG layer, an FSG layer, a CDO layer, anOSG layer or a combination thereof such as a stack structure includingone or more of the foregoing. The oxide layer may include a layer coatedby a spin coating method such as an SOD layer.

A storage node contact plug 603 through the inter-layer dielectric layer602 is formed to be connected to a region in the substrate 601. To bespecific, the inter-layer dielectric layer 602 is etched to form acontact hole exposing the substrate 601. A conductive material is formedto fill the contact hole and then an etch process is performed until asurface of the inter-layer dielectric layer 602 is exposed.

The conductive material may include a transition metal layer, a rareearth metal layer, a transition metal silicide, a rare earth metalsilicide, or an alloy thereof. The conductive material may include apolysilicon layer doped with impurity ions or have a stack structure ofmulti-layers. When the storage node contact plug 603 includes a metallayer (the transition metal, the rare earth metal), a barrier metallayer (not shown) may be additionally formed between the storage nodecontact 603 and the contact hole.

An etch stop layer 604 is formed over the inter-layer dielectric layer602. When the contact hole for a subsequent lower electrode is formed,the etch stop layer 604 stops the etch process to prevent theinter-layer dielectric layer 602 from being damaged. Furthermore, when adip-out process for forming the pillar type capacitor is performed, theetching solution is prevented from flowing into the inter-layerdielectric layer 602 by the etch stop layer 605. Thus, the etch stoplayer 604 includes a material having an etch selectivity ratio with asubsequent sacrificial layer. The etch stop layer 604 may be a nitridelayer including a silicon nitride such as SiN, Si₃N₄.

A sacrificial layer 605 is formed over the etch stop layer 604. In thesacrificial layer 605, a contact hole for the lower electrode is formed.The sacrificial layer 605 may include an oxide layer and may compriseone layer or multi-layers. The oxide layer may be an HDP oxide layer, aBPSG layer, a PSG layer, a BSG layer, a TEOS layer, an USG layer, an FSGlayer, a CDO layer, an OSG layer or a combination thereof such as astack structure of the foregoing. The oxide layer may include a layercoated by a spin coating method such as an SOD layer.

The sacrificial layer 605 and the etch stop layer 604 are etched to forma storage node hole 606 exposing the storage node contact hole 603. Thestorage node hole 606 defines a region where the lower electrode isformed. In detail, mask patterns are formed over the sacrificial layer605, then the sacrificial layer 605 and the etch stop layer 604 areetched using the mask patterns as an etch barrier to form the storagenode hole. For mask patterns, a photoresist layer is coated over thesacrificial layer 605 and patterned to open the region where the storagenode contact hole is formed. A hard mask layer may be additionallyformed before the photoresist layer is formed to secure an etch marginwhich may not be sufficient only with the photoresist layer.

Referring to FIG. 8B, a lower electrode 607 including the nickel layercontaining the impurities is formed over the resultant structure of FIG.8A including the storage node hole 606. The lower electrode 607including the nickel layer containing the impurities is formed through aCVD process or an ALD process. The ALD process may be performed to beapplied to a structure having high step coverage or a big heightdifference. Thus, the ALD process in the timing diagram illustrated inFIG. 3 can be applied to form the structures described above referringto FIGS. 2A to 2C. Preferably, the lower electrode 607 is formed to havethe structure illustrated in FIG. 2A to form the pillar type capacitor.

The lower electrode 607 containing the impurities includes a firstnickel layer containing impurities, a pure nickel layer, and a secondnickel layer containing impurities as the structure illustrated in FIG.2A. The pure nickel layer exhibits a high work function, low leakagecurrent and an excellent adhesion force to other layers. Furthermore,the first and second nickel layers with the impurities are formed overand below the pure nickel layer. Thus, surface roughness of the purenickel layer is improved and the surface oxidation during a subsequentdielectric layer formation process is prohibited.

A thermal treatment process is performed on the lower electrode 607 toincrease crystallinity. The thermal treatment process may be a rapidthermal treatment process or furnace annealing process. A temperaturefor the thermal treatment process varies according to equipment. In thisembodiment, the thermal treatment process is performed at a temperatureof approximately 400 to approximately 800.

Referring to FIG. 8C, a lower electrode pattern 607A remains in thestorage node hole 606, for example, by a planarization process. Theplanarization process may be a CMP process or etch back process.

Referring to FIG. 8D, the sacrificial layer 605 (refer to FIG. 8C) isremoved through a dip-out process. The dip-out process is performedusing a BOE or HF. The etch stop layer 604 prevents the BIE or the HFfrom flowing into the inter-layer dielectric layer 602, therebypreventing a damage to the inter-layer dielectric layer 602 caused bythe dip-out process. As a result, the pillar type lower electrode 607Ais formed.

Referring to FIG. 8E, a dielectric layer 608 is formed over theresultant structure of FIG. 8D including the lower electrode 607A. Thedielectric layer 608 may include a high-k material including, but notlimited to, TiO₂, SrTiO₂ or BaSbTiO₃. The dielectric constant (k) ofTiO₂ is 60 to 100, that of SrTiO₂ is 80 to 100 and that of BaSbTiO₃ is100 to 300. TiO₂, SrTiO₂ and BaSbTiO₃ have low energy band gap and avery high dielectric constant. As described above referring to FIG. 8B,the lower electrode 607 containing the impurities exhibits excellentadhesion force, a high work function, and improved surface roughness andoxidation characteristics of the pure nickel layer. Thus, adeterioration of the dielectric layer 608 with the high-k can beimproved. Furthermore, crystallinity of the dielectric layer 608 canalso be improved by the improved adhesion force.

Thereafter, an upper electrode 609 is formed over the dielectric layer608. The upper electrode 609 is formed by the same manner with that forforming the lower electrode 607A. That is, the upper electrode 609 isformed to include the nickel layer containing the impurities. After theupper electrode 609 is formed, a thermal treatment process is performedfor the same reason as the thermal treatment of the lower electrodepattern 607A.

While embodiments have been described with reference to the pillar typeand the cylinder type capacitors and the method for fabricating thesame, changes and modifications can be made to be applied to a planartype capacitor and a concave type capacitor. Furthermore, changes andmodifications can be made to be applied to any other electrodes in thedevices applying a high-k layer, improving the leakage currentcharacteristics, as well as any other electrodes requiring a lowresistivity and a high work function.

While one or more embodiments been described it will be apparent tothose skilled in the art that various changes and modifications may bemade.

1. An electrode for a semiconductor device, comprising: a nickel layerwith impurities.
 2. The electrode of claim 1, wherein the impuritiesinclude carbon (C) or hydrogen (H).
 3. The electrode of claim 1, whereina concentration of the impurities in the nickel layer with impuritiesranges from approximately 5% to approximately 50%.
 4. The electrode ofclaim 1, wherein the electrode is a gate electrode.
 5. An electrode fora semiconductor device, comprising: a combination of a pure nickel layerand a nickel layer with impurities.
 6. The electrode of claim 5, whereinthe pure nickel layer and the nickel layer with impurities are formed tohave a stack structure.
 7. The electrode of claim 5, wherein thecombination of the pure nickel layer and the nickel layer withimpurities has a stack structure of a first nickel layer withimpurities, a pure nickel layer, and a second nickel layer withimpurities.
 8. The electrode of claim 5, wherein the impurities includecarbon (C) or hydrogen (H).
 9. The electrode of claim 5, wherein aconcentration of the impurities in the nickel layer with impuritiesranges from approximately 5% to approximately 50% of the nickel layer.10. The electrode of claim 5, wherein the electrode is a gate electrode.11. A capacitor, comprising: a first electrode; a dielectric layer; anda second electrode, wherein one of the first electrode and the secondelectrode includes a nickel layer with impurities.
 12. The capacitor ofclaim 11, wherein one of the first electrode and the second electrodeincludes a pure nickel layer and a nickel layer with impurities.
 13. Thecapacitor of claim 12, wherein the nickel layer with impurities isformed to be in contact with the dielectric layer.
 14. The capacitor ofclaim 12, wherein one of the first electrode and the second electrodehas a stack structure of a first nickel layer with impurities, a purenickel layer, and a second nickel layer with impurities.
 15. Thecapacitor of claim 11, wherein the impurities include carbon (C) orhydrogen (H).
 16. The capacitor of claim 11, wherein a concentration ofthe impurities in the nickel layer with impurities ranges fromapproximately 5% to approximately 50% of the nickel layer withimpurities.
 17. The capacitor of claim 11, wherein the first electrodeor the second electrode is a plate type, a concave type, a cylindertype, or a pillar type.